Converter circuit for a limiter receiver structure and method for converting a signal in a limiter receiver structure

ABSTRACT

The present invention relates generally to a converter circuit with a limiter to convert an analog reception signal into a value-discrete limiter signal. An evaluation circuit determines a zero crossing distance signal from the temporal distances between successive zero crossings of the limiter signal. A synthesis circuit calculates a digital processing signal whose zero crossings correspond to those of the limiter signal and whose pulse shape has a smaller spectral width than a rectangular pulse.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of PCT/DE03/04278, filed on Dec. 23,2003, which was not published in English, which claims the benefit ofthe priority date of German Patent Application No. DE 103 00 938.8,filed on Jan. 13, 2003, the contents of which both are hereinincorporated by reference in their entireties.

FIELD OF THE INVENTION

The invention relates to a converter circuit for processing an analogfrequency- or phase-modulated reception signal for a limiter receiverstructure and a method for the signal conversion of an analog frequency-or phase-modulated reception signal in a limiter receiver structure.

BACKGROUND OF THE INVENTION

So-called limiter receiver structures are used for outlay-favorableimplementation of receivers for frequency- or phase-modulated signalswith a constant envelope such as, for example, GFSK (Gaussian FrequencyShift Keying) signals. The functional principle of a limiter receiverstructure is based on the fact that the essential portion of theinformation of a frequency- or phase-modulated signal lies in thefrequency or the phase and thus in the zero crossings of the signal. Theanalog-to-digital conversion of the reception signal is effected in alimiter receiver structure by means of a threshold value decision (whichis performed by the limiter) and a subsequent sampling of thevalue-discrete time-continuous rectangular signal output by the limiter.Since the entire useful information of the signal lies in the zerocrossings in the signal path downstream of the limiter, a high samplingrate T_(z) ⁻¹ is necessary in order to detect the zero crossings withthe necessary accuracy. In order to avoid, during the sampling, spectraloverlaps (aliasing) of higher harmonic spectral components and thusextinction of information, the sampling rate T_(z) ⁻¹ has to be chosento be significantly greater than the bandwidth B of the signal receivedby the limiter. In other words, the minimum sampling rate required fromthe standpoint of information theory (said rate being determined by thebandwidth B of the signal received by the limiter) is considerably lowerthan the sampling rate T_(z) ⁻¹ used.

Afterward, from the digital signal generated by the sampling, by meansof a plurality of filter stages, the higher harmonic components of thesignal are eliminated, the signal rate is decimated, and a digitalsignal equivalent to the GFSK signal is generated by means of ademodulation. The elimination of the higher harmonic components of thesignal has to be effected with the high sampling rate T_(z) ⁻¹ and makeshigh requirements of the filters used in the signal path downstream ofthe sampling. In practice, complicated filter cascades with interposeddecimation stages will be used for the signal reconstruction. Ahigh-power consumption occurs on account of the high sampling rate T_(z)⁻¹.

The article “Low-Power Design of a Digital FM Demodulator Based onZero-Cross Detection at IF”, N. Ismailoglu et al., IEEE VehicularTechnology Conference, Sep. 19-22, 1999, pages 810 to 813, discloses alimiter discriminator circuit in which a digital zero crossing detectoris arranged in the signal path downstream of the sampling. The zerocrossing detector generates a signal specifying the instants of the zerocrossings of the signal output by the limiter through generation of alogic “1”. For demodulation of the signal output by the zero crossingdetector, use is made of a fourth-order sinc cube decimation filter anda subsequent lowering of the sampling rate by the factor 4.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentone or more concepts of the invention in a simplified form as a preludeto the more detailed description that is presented later.

The invention is based on the object of providing a converter circuitfor processing an analog frequency- or phase-modulated reception signalfor a limiter receiver structure which enables a demodulation of theconverted signal using simpler filter structures. Furthermore, theinvention aims to specify a method for processing an analog frequency-or phase-modulated reception signal in a limiter receiver structure bymeans of which it is possible to generate a processing signal that canbe demodulated expediently in respect of complexity. In particular, theintention is, moreover, to be able to obtain a low power consumption inthe converter circuit and subsequent circuit sections (demodulator).

The converter circuit according to the invention comprises a limiter,wherein the limiter converts an analog reception signal into atime-continuous, value-discrete limiter signal comprising a sequence ofrectangular pulses. An evaluation circuit is coupled to the limiter,wherein the evaluation circuit detects the temporal distances between ineach case two successive zero crossings of the limiter signal andoutputs a zero crossing distance signal. Furthermore, the convertercircuit comprises a signal synthesis circuit, which receives the zerocross distance signal and, in a manner dependent on the latter,generates a value- and time-discrete processing signal for the signaldemodulation whose zero crossings correspond to the zero crossings ofthe limiter signal and whose pulse shape used for the signal synthesishas a smaller spectral width than a rectangular pulse of correspondingwidth.

In one advantageous embodiment of the present invention, what isachieved by means of the signal synthesis circuit is that, instead ofthe rectangular pulses implicitly predetermined by the limiter for thesignal processing coupled to the converter circuit, use is made ofpulses with a signal shape which have a smaller spectral width thanrectangular pulses. On account of the better spectral characteristic,the requirements made of the filter units and thus also the complexitythereof decrease.

In one embodiment of the present invention, the pulse shape used in thesignal synthesis may be chosen optimally in accordance with thepost-processing that follows in the signal path coupled to the convertercircuit. However, a particular refinement of the invention ischaracterized in that the signal synthesis circuit uses a triangularpulse as pulse shape. A triangular pulse has a substantially betterspectral characteristic than a rectangular pulse, so that this choicemakes it possible to obtain a large gain in complexity in the subsequentunits (filters). A further advantage of using a triangular pulse is thatthe signal values of the triangular pulse can be calculated by means ofsimple linear operations.

A further advantageous refinement of the invention is characterized inthat the temporal distances between in each case two successive zerocrossings of the limiter signal are detected with a time accuracy T_(z),and in that the processing signal has a sampling rate T_(s) ⁻¹ that isless than T_(z) ⁻¹. This permits the baseband signal processing(filtering including demodulation) to be performed with a significantlylower sample rate T_(s) ⁻¹ even within the converter circuit (forexample, after the determination of the zero crossings) and alsodownstream of the converter circuit). A significant reduction of thepower consumption is achieved by means of this measure.

A further advantageous refinement of the invention is characterized inthat the evaluation circuit comprises a zero crossing detector and acounter coupled to the zero crossing detector. In this case, only thecounter has to be operated with the (high) sampling rate or clockfrequency T_(z) ⁻¹. The pulse generation in the signal synthesis circuitcan already be effected in energy-saving fashion on the time base givenby the reduced sampling rate T_(s) ⁻¹. For this purpose, the signalsynthesis circuit preferably comprises an interpolator which, in amanner dependent on the zero crossing distance signal synthesizes theprocessing signal at the support points determined by the sampling rateT_(s) ⁻¹ using the predetermined pulse shape.

To the accomplishment of the foregoing and related ends, the inventioncomprises the features hereinafter fully described and particularlypointed out in the claims. The following description and annexeddrawings set forth in detail certain illustrative aspects andimplementations of the invention. These are indicative, however, of buta few of the various ways in which the principles of the invention maybe employed. Other objects, advantages and novel features of theinvention will become apparent from the following detailed descriptionof the invention when considered in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in more detail in the following textwith reference to a number of drawing figures, in which:

FIG. 1 is a converter circuit with a limiter in accordance with theprior art;

FIG. 2 is a converter circuit with a limiter according to the invention;

FIG. 3 a is an illustration of the signal profile of an input signal forthe converter circuit according to the invention;

FIG. 3 b is an illustration of the signal profile of a time-continuous,value-discrete signal output by the limiter;

FIG. 3 c is an illustration of the signal profile of a digital countingsignal output by the counter;

FIG. 4 is an illustration of the signal profile of a value- andtime-discrete processing signal output by the converter circuitaccording to the invention;

FIG. 5 is a circuit diagram of the pulse synthesis stage illustrated inFIG. 2; and

FIG. 6 is a circuit diagram of a radio receiver with a limiter receiverstructure.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a converter circuit WS for the analog-digital conversion offrequency- or phase-modulated signals in a limiter receiver structureaccording to the prior art. The converter circuit WS comprises a limiterL, the output of which is connected to the input of a sampling stage AS.The sampling stage AS is operated with a sampling frequency T_(z) ⁻¹.The output signal of the sampling stage AS is fed to a basebandprocessing circuit BS which carries out a filtering and signaldemodulation.

The functioning of the circuit illustrated in FIG. 1 is as follows:

The limiter L carries out a threshold value decision of the analogreception signal a(t). A section of the temporal profile of the analogreception signal a(t) is illustrated in FIG. 3 a. The analog receptionsignal a(t) is a sinusoidal signal having a varying period length onaccount of the frequency or phase modulation. If, for example, atwo-value (binary) modulation alphabet is used at the transmitter end,the modulated reception signal a(t) has two different period lengths.

The limiter L performs a threshold value decision. The output signallim(t) of the limiter L is determined as follows:lim(t)=−1 if a(t)<0lim(t)=+1 if a(t)>0.

The output signal lim(t) of the limiter L, comprising a sequence ofrectangular pulses, is sampled by the sampling stage AS with a samplingrate T_(z) ⁻¹. The sampling time T_(z) determines the time resolutionfor determining the zero crossing of lim(t). On account of the poorspectral properties of rectangular pulses, T_(z) ⁻¹ must besubstantially greater than the bandwidth B of the signal a(t).

The digital signal output by the sampling stage AS is designated byp(nT_(z)). In this case nT_(z) specifies the discrete time in units n ofthe sampling time duration T_(z). The digital signal p(nT_(z)) isforwarded to the baseband processing circuit BS, in which, as known inthe prior art, the higher harmonic components of the signal areeliminated by filtering and a demodulated signal is generated.

FIG. 2 shows a limiter receiver structure with a converter circuit WS′according to the invention.

The converter circuit WS′ has a limiter L, a zero cross detector NDconnected downstream of the limiter L, a counter CN connected downstreamof the zero crossing detector ND, and a pulse synthesis stage PSYconnected downstream of the counter CN. The output of the pulsesynthesis stage PSY is forwarded to a baseband processing circuit BS′.The zero crossing detector ND and the counter CN form an evaluationcircuit AW.

In terms of construction and functioning, the limiter L is identical tothe limiter L described with reference to FIG. 1. The signal lim(t)output by the limiter L is illustrated in FIG. 3 b. The duration of therectangular pulses corresponds to the respective zero crossing distancesT_(l−1), T_(l), T_(l+1) of the reception signal a(t). The zero crossingsof the time-continuous, value-discrete output signal lim(t) of thelimiter L are determined in the zero crossing detector ND. If a zerocrossing is identified, then the zero crossing detector ND outputs asignal start_z. This zero crossing signal start_z starts the counter CNanew in each case. The counter CN is operated with the clock frequencyor sampling rate T_(z) ⁻¹. In each case upon the next activation by thesignal start_z, the current counting result Z_(l) (corresponding to thezero cross distance T_(l)) is present at the output of the counter CNuntil the end of the current counting period. The output signal cnt ofthe counter CN and also the current internal counter reading (dashedline) are illustrated in FIG. 3 c. The time granularity required formeasuring the zero crossing time distances is T_(z) and is of the sameorder of magnitude as the sample frequency T_(z) of the prior artcircuit shown in FIG. 1.

As can be seen from FIGS. 3 a to 3 c, the magnitude of the (maximum)counts Z_(l−1), Z_(l), Z_(l+1) corresponds to the time durationsT_(l−1), T_(l), T_(l+1) of the time intervals L−1, l and l+1 defined byzero crossings.

On the basis of these zero crossing time distances T_(l−1), T_(l),T_(l+1) determined with the time granularity T_(z), the pulse synthesisstage PSY generates a digital processing signal p(nT_(s)) from a basicpulse. By way of example, a triangular pulse may be used as the basicpulse, as illustrated in FIG. 4. The digital processing signal p(nT_(s))may be generated by means of an interpolator, which, in a mannerdependent on the zero crossing time distances T_(l−1), T_(l), T_(l+1)output by the counter CN in the form of the counters Z_(l−1), Z_(l),Z_(l+1), calculates the processing signal at the support pointsdetermined by means of a time base T_(s) using triangular pulses. Thetime base T_(s) with respect to which the digital processing signalp(nT_(s)) is generated may be chosen arbitrarily, in principle, acertain minimum time resolution (maximum sampling time duration T_(s))having to be ensured on account of the requirements by the subsequentsignal processing and also on account of requirements appertaining tosignal theory (satisfying the sampling theorem).

It is pointed out that the time resolution T_(s) is now no longerdetermined by the accuracy requirements of the zero crossings, butrather depends on the spectral properties of the pulse used forsynthesis of the digital processing signal p(nT_(s)) and also thesubsequent baseband signal processing in the baseband processing stageBS′.

This makes it possible to perform the baseband processing in thebaseband processing stage BS′ at a significantly lower sampling rateT_(s) ⁻¹ after the determination of the zero crossings with the timeaccuracy T_(z). The requirements made of the complexity of the basebandprocessing stage BS′ thus decrease.

It is furthermore pointed out that even the time-discrete processingsignal p(nT_(s)) is generated with the low processing rate T_(s). Thatis to say that the individual basic pulses are not generated with a highsampling rate (e.g. T_(z) ⁻¹) and decimated, rather they are calculatedby means of interpolation directly on the minimum required time basisT_(s). This is because the pulse synthesis stage PSY accepts the countsZ_(l−1), Z_(l), s_(l+1) of the output signal cnt of the counter CN withits own (slow) clock T_(s). Therefore, the pulse synthesis stage PSY canalso be implemented with very low complexity.

FIG. 5 shows an implementation—favorable in respect of complexity—of thepulse synthesis stage PSY for generating triangular pulses with uniformmaximum height C. The pulse synthesis stage PSY comprises a counter CN1,a comparator COMP connected downstream of the counter, a table storeTAB, an accumulator AC and a multiplier M.

It is assumed that the count Z_(l) is present as an integral multiple ofthe sample time Ts. The integral multiple N is defined by the equationN=T_(s)/T_(z). The following relationship then results for the outputvalues p(nT_(s)) of the triangular pulse:

${p( {nT}_{s} )} = \{ \{ \begin{matrix}{2{C \cdot n \cdot {N/Z_{1}}}} & {{{for}\mspace{14mu} 0} < n < {Z_{1}/( {2N} )}} \\{{2C} - {2{C \cdot n \cdot {N/Z_{1}}}}} &  {{{for}\mspace{14mu}{Z_{1}/( {2N} )}} < n < {Z_{1}/N}} )\end{matrix}  $

The counter CN1 generates the value n representing the discrete time.The comparator COMP checks whether n<Z_(l)/(2N), i.e. whether the upperor the lower expression of the equation specified above has to be usedfor generating the signal values. The comparator COMP outputs a controlsignal S having the value S=1 if the inequality n<Z_(l)/(2N) issatisfied. Otherwise, S=0 holds true.

The factor N/Z_(l) is designated by C₀. Since only a finite number offactors N/Z_(l) exist, these can be calculated in advance and stored inthe table store TAB. The currently required value C₀ is read out fromthe table store TAB in a manner dependent on the counting result Z_(l)and forwarded to the accumulator AC. At the system clock rate T_(s) ⁻¹of the pulse synthesis stage PSY, the accumulator AC calculates theexpression p=C₀·n for S=1 or the expression p=1−C₀·n for S=0. The pulseshape is thus generated with the correct pulse length. The maximumamplitude C of the triangular pulse is determined by multiplication bythe factor 2C. The multiplication is carried out by the multiplier M. Cmay be chosen in accordance with the requirements of the subsequentunits (baseband processing BS′).

FIG. 6 shows, in an exemplary manner, the construction of a receivercircuit according to the limiter discriminator principle as disclosedfor example in the German patent application DE 101 03 479 A1. The knownconverter circuit WS shown in FIG. 6 corresponds to the convertercircuit WS illustrated in FIG. 1.

In accordance with FIG. 6, a radio signal is captured by an antenna Aand fed via an input filter E to a low noise input amplifier LNA (LowNoise Amplifier). The input amplifier LNA amplifies the radiofrequencyantenna signal with an adjustable gain. After the low noiseamplification, the amplified signal is converted to an intermediatefrequency. For this purpose, the output signal of the low noiseamplifier LNA is fed to two mixers M1 and M2. The mixers M1 and M2 areoperated in a known manner, with a phase offset of 90°, with a mixingfrequency which is derived from a local oscillator (not illustrated).The two signals used for operating the mixers M1 and M2 correspond intheir time dependence to cos(ω₀t) and sin(ω₀t), where ω₀ designates theangular frequency assigned to the oscillator frequency and t designatesthe time.

Inphase (I) and quadrature (Q) signals in the intermediate frequency areavailable at the outputs of the mixers M1 and M2, respectively.

The outputs of the two mixers M1 and M2 are fed to an I and respectivelya Q signal input of an analog channel selection filter KSF serving forimage frequency suppression. By means of the channel selection filterKSF, a specific frequency channel is selected and the desired usefulsignal is thereby filtered out from the broadband signal-interferencesignal mixture present on the input side.

The two I and Q signal components are output with the bandwidth of theuseful channel at two outputs A1, A2 of the channel selection filterKSF.

In the case of a receiver circuit according to the invention based onthe limiter discriminator principle, the known converter circuit WS isreplaced by the converter circuit WS′ according to the invention asillustrated in FIG. 2. Furthermore, the simplified baseband processingcircuit BS′ is used instead of BS (illustrated in two-channel fashion inFIG. 6). The analog reception signal a(t) thus corresponds to the Isignal component and the Q signal component at the outputs A1 and A2,respectively.

For the baseband processing/demodulation, it is possible, by way ofexample, to use the algorithm described in the document DE 101 03 479A1, which is hereby incorporated by reference in the content of thepresent document.

While the invention has been illustrated and described with respect toone or more implementations, alterations and/or modifications may bemade to the illustrated examples without de-parting from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and the claims, such termsare intended to be inclusive in a manner similar to the term“comprising”.

1. A converter circuit for processing an analog reception signal for alimiter receiver structure, comprising: a limiter configured to convertthe analog reception signal into a time-continuous, value-discretelimiter signal characterized by a sequence of rectangular pulses; anevaluation circuit coupled to the limiter, wherein the evaluationcircuit detects the temporal distances between two successive zerocrossings of the limiter signal and outputs a zero crossing distancesignal in response to the detection of the temporal distances; and asignal synthesis circuit receiving the zero crossing distance signal andgenerating a value- and time-discrete processing signal, wherein thezero crossings of the processing signal correspond to the zero crossingsof the limiter signal and the pulse shape used for the signal synthesishas a smaller spectral width than a rectangular pulse of correspondingwidth.
 2. The converter circuit of claim 1, wherein the signal synthesiscircuit uses a triangular shaped pulse.
 3. The converter circuit ofclaim 1, wherein the evaluation circuit detects the temporal distancesbetween each of two successive zero crossings of the limiter signal witha time accuracy, and wherein the processing signal has a sampling ratethat is less than a clock frequency.
 4. The converter circuit of claim3, wherein the evaluation circuit comprises a zero crossing detectorcoupled to a counter.
 5. The converter circuit of claim 1, wherein thesignal synthesis circuit has an interpolator that synthesizes theprocessing signal at support points determined by the sampling rateusing the predetermined pulse shape.
 6. The converter circuit of claim1, wherein the evaluation circuit detects the temporal distances betweentwo successive zero crossings of the limiter signal with a timeaccuracy, and wherein the processing signal has a sampling rate that isless than a clock frequency.
 7. The converter circuit of claim 6,wherein the evaluation circuit comprises a zero crossing detectorcoupled to a counter.
 8. A method for converting an analog receptionsignal in a limiter receiver structure, the method comprising:generating a limited, time-continuous, value-discrete limiter signalcharacterized by a sequence of rectangular pulses from an analogreception signal; determining the temporal distances between twosuccessive zero crossings of the limiter signal; and synthesizing avalue- and time-discrete processing signal based on the temporaldistances determined between successive zero crossings of the limitersignal, wherein the zero crossings of the processing signal correspondto the zero crossings of the limiter signal and the pulse shape used forthe signal synthesis has a smaller spectral width than a rectangularpulse of corresponding width.
 9. The method of claim 8, wherein atriangular pulse is used as pulse shape.
 10. The method of claim 8,wherein the temporal distances between two successive zero crossings ofthe limiter signal are determined with a time accuracy and theprocessing signal is synthesized with a sampling rate that is less thana clock frequency.
 11. The method of claim 10, wherein the temporaldistance between two successive zero crossings of the limiter signal aredetected.
 12. The method of claim 8, wherein the value-and time-discreteprocessing signal is calculated in a manner dependent on the temporaldistances between two zero crossings by an interpolation of thepredetermined pulse shape at the support points determined by thesampling rate.
 13. A converter circuit for processing an analogreception signal for a limiter receiver structure, comprising: a limiterconfigured to convert the analog reception signal into atime-continuous, value-discrete limiter signal characterized by asequence of rectangular pulses; an evaluation circuit coupled to thelimiter, wherein the evaluation circuit detects the temporal distancesbetween two successive zero crossings of the limiter signal and outputsa zero crossing distance signal in response to the detection of thetemporal distances; and a signal synthesis circuit receiving the zerocrossing distance signal and generating a value- and time-discreteprocessing signal, wherein the zero crossings of the processing signalcorrespond to the zero crossings of the limiter signal and the pulseshape used for the signal synthesis has a smaller spectral width than atriangular pulse of corresponding width.
 14. The converter circuit ofclaim 13, wherein the signal synthesis circuit has an interpolator thatsynthesizes the processing signal at support points determined by thesampling rate using the predetermined pulse shape.